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Depletion and Pinchoff The JFET works because the voltage at the gate causes an electric field that interferes, more or less, with the flow of charge carriers along the channel A simplified drawing of the situation for an N-channel device is shown in Fig 23-3 As the drain voltage ED increases, so does the drain current ID, up to a certain level-off value This is true as long as the gate voltage EG is constant, and is not too large negatively But as EG becomes increasingly negative (Fig 23-3A), a depletion region (shown as a solid dark area) begins to form in the channel Charge carriers cannot flow in this region; they must pass through a narrowed channel The more negative EG becomes, the wider the depletion region gets, as shown in drawing B Ultimately, if the gate becomes negative enough, the depletion region completely obstructs the flow of charge carriers This condition is called pinchoff, and is illustrated at C JFET Biasing Two biasing methods for N-channel JFET circuits are shown in Fig 23-4 In Fig 23-4A, the gate is grounded through resistor R2 The source resistor, R1, limits the current through the JFET The drain current, ID, flows through R3, producing a voltage across this resistor The ac output signal passes through C 2 In Fig 23-4B, the gate is connected through potentiometer R2 to a voltage that is negative with respect to ground Adjusting this potentiometer results in a variable negative EG between R2 and R3 Resistor R1 limits the current through the JFET The drain current, ID, flows through R4, producing a voltage across it The ac output signal passes through C 2 In both of these circuits, the drain is positive relative to ground For a P-channel JFET, reverse the polarities in Fig 23-4 Typical power-supply voltages in JFET circuits are comparable to those for bipolar transistor circuits The voltage between the source and drain, abbreviated ED, can range from about 3 V to 150 V dc; most often it is 6 to 12 V dc The biasing arrangement in Fig 23-4A is preferred for weak-signal amplifiers, low-level amplifiers, and oscillators The scheme at B is more often employed in power amplifiers having substantial input signal amplitudes.

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Consider two points P1 and P2 Let the vector v denote the directed line segment from P1 to P2 Relative to 1 , v can be described as 1 x2 x1 v = y2 y1 z2 z1 1 1 x2 x1 = y2 y1 z2 z1 1 x2 xO = yO + R1 y2 2 zO z2 1 x1 xO yO + R1 y1 2 zO z1

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The graph of Fig 23-5 shows ID as a function of EG for a hypothetical N-channel JFET The drain voltage, ED, is assumed to be constant When EG is fairly large and negative, the JFET is pinched off, and no current flows through the channel As EG gets less negative, the channel opens up, and ID begins flowing As EG gets still less negative, the channel gets wider and ID increases As EG approaches the point where the S-G junction is at forward breakover, the channel conducts as well as it possibly can If EG becomes positive enough so the S-G junction conducts, some of the current in the channel leaks out through the gate This is usually an unwanted phenomenon

CHAPTER 2 REFERENCE FRAMES 2 2 x1 x2 = R1 y2 y1 2 z2 z1 v1 = R1 v2 2 (220)

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Eqn (220) is the vector transformation between coordinate systems This relation is valid for any vector quantity As discussed in detail in [95], it is important to realized that vectors, vector operations, and relations between vectors are invariant relative to any two particular coordinate representations as long as the coordinate systems are related through eqn (220) This is important, as it corresponds to the intuitive notion that the physical properties of a system are invariant no matter how we orient the coordinate system in which our analysis is performed In the discussion of this section, the two frames have been considered to have no relative motion Issues related to relative motion will be critically important in navigation systems and are discussed in subsequent sections Throughout the text, the notation Rb will denote the rotation matrix a transforming vectors from frame a to frame b Therefore, vb v where Ra = Rb a b

The FET Amplifies Voltage The best amplification for weak signals is obtained when EG is such that the slope of the curve in Fig 23-5 is the greatest This is shown roughly by the range marked X For power amplification, however, results are often best when the JFET is biased at or beyond pinchoff, in the range marked Y In either circuit shown in Fig 23-4, ID passes through the drain resistor Small fluctuations in EG cause large changes in ID, and these variations in turn produce wide swings in the dc voltage across R3 (in the circuit at A) or R 4 (in the circuit at B) The ac part of this voltage goes through capacitor C2, and appears at the output as a signal of much greater ac voltage than that of the input signal at the gate Drain Current versus Drain Voltage Do you suspect that the current ID, passing through the channel of a JFET, increases in a linear manner with increasing drain voltage ED This seems reasonable, but it is not what usually happens Instead, ID rises for awhile as ED increases steadily, and then ID starts to level off The current ID can be plotted graphically as a function of ED for various values of EG When this is done, the result is a family of characteristic curves for the JFET The graph of Fig 23-6 shows a family of characteristic

(221) (222)

curves for a hypothetical N-channel device The graph of ID versus EG, one example of which is shown in Fig 23-5, is also an important specification that engineers consider when choosing a JFET for a particular application

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